A lateral power MOSFET is basically a metal oxide semiconductor field effect transistor fabricated with coplanar drain and source regions. FIG. 1A shows a lateral power MOSFET device 100 in the prior art. The device 100 is formed on a p-type substrate 101 and another p-layer 113 is epitaxially grown on the substrate 101. A high-voltage P-well 115 is adjacent a high-voltage N-well 103 in the epitaxially grown p-layer 113. An N+ source 117 is positioned in the high-voltage P-well 115 such that the N+ source 117 is not immediately adjacent the high-voltage N-well 103, and an N+ drain 105 is positioned in the high-voltage N-well 103. Dielectrics 121 are formed to isolate and define areas such as the N+ source 117 and the N+ drain 105 of the device 100. A gate dielectric 111 and a gate electrode 110 are formed extending from the source 117 to a portion of the field dielectric 107. The device 100 also includes a P+ area 119 located in the high-voltage P-well 115. Applying a positive voltage to the gate electrode 110 induces a current to flow through the channel from the N+ source 117 into the high-voltage N-well 103 to be collected at the N+ drain 105.
A problem with this type of lateral power MOSFET is that it cannot maintain a low on-resistance when a high voltage is passed through the lateral power MOSFET. The on-resistance is the power of the current that is transformed into heat as the current travels through the device. The larger the on-resistance of the device, the less efficient the device. Accordingly, it is desired to reduce this resistance as much as possible for a more efficient device.
FIG. 1B illustrates another device 150 known in the prior that is designed to mitigate this problem. Device 150 is similar to device 100 of FIG. 1A, wherein like reference numerals refer to like elements, except a field ring 109 has been added. The field ring 109 works to reduce the surface electrical field and improves the depletion capability of the drift region. As a result, the doping concentration of the drift region can be increased and the on-resistance of the device 100 can be decreased.
Another problem with the prior art device 100 (shown in FIG. 1A) and the prior art device 150 (shown in FIG. 1B) is that the breakdown voltage is not as high as desired. The breakdown voltage is the voltage below which the respective device (such as a MOS capacitor or reverse biased p-n junction) may operate. When a voltage greater than the breakdown voltage is applied, catastrophic and irreversible damage is done to the device, rendering the devices commercially useless and requiring the device to be replaced. Accordingly, increasing the breakdown voltage is highly desirable.
FIG. 2 is a lateral power MOSFET designed to increase the breakdown voltage of the device 200. In FIG. 2 the field dielectrics have been removed from view for clarity. In this device 200 partition regions 201 have been placed into the high-voltage N-well 103, as shown in FIG. 2, such that there are areas of alternating conductivity in the high-voltage N-well region. This type of configuration is known in the art as a superjunction. The partition regions 201 work to increase the horizontal depletion capability of the drift region, which allows for a higher concentration of doping in the drift region. This helps to increase the breakdown voltage and works to reduce the specific on-resistance of the device.
Those prior art systems, however, have difficulties sustaining high voltage and low on-resistance. Therefore, an improved lateral power MOSFET is needed for a reduced on-resistance, a higher breakdown voltage, and a better stability against baking and packaging processes.